In wireless communication, it is required to utilize various frequency bands effectively, and accordingly, there is a demand for a wireless apparatus compatible with various frequencies. Regarding a transmitter, a 1-bit digital transmitter, in which an analog circuit only compatible with a fixed frequency is replaced with a digital circuit independent of frequency, has been studied.
As a related technology, Non-Patent Literature 1 describes a technology related to a delta sigma Digital-to-Analog Converter (ΔΣ DAC) used in a modulator of a 1-bit digital transmitter.
In recent years, carrier frequency has shifted to a high frequency band in wireless communication, and a demand for delta sigma (ΔΣ) modulation to operate at high speed (high-speed bit rate) has been increasing accordingly. An operating frequency of a ΔΣ modulator is, for instance, at most, twice a carrier frequency in case of low-pass ΔΣ modulation, the same as a carrier frequency in case of envelope ΔΣ modulation, and in general, it is proportional to a carrier frequency regardless of a ΔΣ modulation scheme.
Regarding high-speed operation of first-order ΔΣ modulation, an arrangement that achieves high-speed operation by eliminating, for instance, carry propagation delay using pipeline processing is known as disclosed in Non-Patent Document 1. FIG. 1, which is taken from FIG. 5 of Non-Patent Document 1, illustrates a first-order two-channel interleaved MASH (multi-stage noise shaping) stage. Each MASH consists of five pipeline stages of 2-bit integrators and one 3-bit forward pipeline stage. Each 2-bit integrator pipeline uses four 1-bit carry select adders. Adders A1 and A2 form Integrator 0, while Adders A3 and A4 form Integrator 1. A flip-flop FF is a D flip-flop that samples a value of a data terminal D at a rising edge (falling edge of a complementary clock clk−) of a clock signal clk and outputs a result from an output terminal Q. A NOR gate outputs a fixed High level when a reset signal rst supplied to one of input terminals is at a Low level, and outputs an inverted a value of the other input terminal when the reset signal rst is at a High level.
Non-Patent Literature 2 discloses a technology related to a 1-bit digital transmitter, an operation frequency of which is confirmed up to 28 GHz (Giga Hertz), in an FPGA (Field-Programmable Gate Array) using combination of a high-speed scheme such as time-interleaved configuration.    [Non-Patent Literature 1]    Ameya Bhide, Omid Esmailzadeh Najari, Behzad Mesgarzadeh, and Atila Alvandpour, “An 8-GS/s 200-MHz Bandwidth 68-mW ΔΣ DAC in 65-nm CMOS”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: EXPRESS BRIEFS, vol. 60, no. 7, pp. 387-391, Jul. 2013.    [Non-Patent Literature 2]    Masaaki Tanio, Shinichi Hori, Noriaki Tawa, Tomoyuki Yamase, and Kazuaki Kunihiro, “An FPGA-based All-Digital Transmitter with 28-GHz Time-Interleaved Delta-Sigma Modulation”, IEEE IMS Symp, pp. 1-4, May 2016.